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ts3005 page 1 ? 2014 silicon laboratories, inc. all rights reserved. features ? ultra low supply current: 1.35 a at 49hz ? supply voltage operation: 1.55v to 5.25v ? single resistor sets fout at 50% duty cycle ? 3-pin user-programmable fout period: ? 1.7ms t fout 33hrs ? fout period accuracy: 3% ? fout period drift: 0.02%/oc ? single resistor sets output frequency ? separate pwm control and buffered output ? fout/pwmout output driver resistance: 160? applications portable and battery-powered equipment low-parts-count na nopower oscillator compact micropower replacement for crystal and ceramic oscillators micropower pulse-width modulation control micropower pulse-position modulation control micropower clock generation micropower sequential timing description the ts3005 is a single-supply, second-generation oscillator/timer fully specifi ed to operate at a supply voltage range of 1.55v to 5.25v while consuming less than 1.5 a(max) supply current. requiring only a resistor to set the base output frequency (or output period) at 49hz (or 20.5ms) with a 50% duty cycle, the ts3005 timer/oscillator is compact, easy-to-use, and versatile. optimized for ultra-long life, low frequency, battery-powered/portable applications, the ts3005 joins the ts3001, ts3002, ts3003, ts3004, and ts3006 in the cmos timer family of ?nanowatt analog?? high-performance analog integrated circuits. the ts3005 output period can be user-adjusted from 1.7ms to 33hrs without additional components. in addition, the ts3005 represents a 25% reduction in pcb area and a factor-of-10 lower power consumption over other cmos-based integrated circuit oscillators/timers. when comp ared against industry- standard 555-timer-based products, the ts3005 offers up to 84% reduction in pcb area and over three orders of magnitude lower power consumption. the ts3005 is fully specified over the -40c to +85c temperature range and is available in a low-profile, 10-pin 3x3mm tdfn package with an exposed back-side paddle. a 1.55v to 5.25v, 1.35a, 1.7ms to 33hrs silicon timer typical application circuit ts3005, 5 weeks and 5 days counter circuit
ts3005 page 2 ts3005 rev. 1.0 absolute maximum ratings v dd to gnd................................................................. -0.3v to +5.5v pwm_cntrl to gnd ................................................ -0.3v to +5.5v fout, pwmout to gnd .......................................... -0.3v to +5.5v rset to gnd ............................................................. -0.3v to +2.5v cpwm to gnd ........................................................... -0.3v to +5.5v fdiv to gnd .............................................................. -0.3v to +5.5v continuous power dissipation (t a = +70c) 10-pin tdfn (derate at 13.48mw/c above +70c) ... 1078mw operating temperature range ................................. -40c to +85c storage temperature range .................................. -65c to +150c lead temperature (soldering, 10s) ...................................... +300c electrical and thermal stresses beyond those listed under ?absolute maximum ratings? ma y cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other condition beyond those indicated in the op erational sections of the specifications is not implied. ex posure to any absolute maximum rating conditions for extended periods may affect device reliability and lifetime. package/ordering information order number part marking carrier quantity ts3005itd1033 3005i tape & reel ----- TS3005ITD1033T tape & reel 3000 lead-free program: silicon labs supplies only lead-free packaging. consult silicon labs for produ cts specified with wider oper ating temperature ranges.
ts3005 ts3005 rev. 1.0 page 3 electrical characteristics v dd = 3v, v pwm_cntrl = v dd , r set = 4.32m? , r load(fout) = open circuit, c load(fout) = 0pf, c load(pwm) = 0pf, c pwm = 47pf, fdiv2:0 = 000 unless otherwise noted. values are at t a = 25c unless otherwise noted. see note 1. parameter symbol conditions min typ max units supply voltage v dd 1.55 5.25 v supply current i dd cpwm = v dd 1.35 1.5 a -40c t a 85c 1.9 1.47 1.7 -40c t a 85c 2.1 fout period t fout 19.95 20.5 21.05 ms -40c t a 85c 19.4 21.5 fout period line regulation ? t fout /v 1.55v v dd 5.25v 0.17 %/v fout duty cycle 49 51 % fout period temperature coefficient ? t fout /? t 0.02 %/c pwmout duty cycle dc(pwmout) 0.08 0.12 % v pwm _ cntrl = 0v 0.02 0.03 pwmout duty cycle line regulation dc(pwmout)/v 1.55v < v dd < 5.25v, fdiv2:0 = 000 -3 % c pwm sourcing current i cpwm fdiv2:0 = 000, 001 930 1050 na -40c t a 85c 810 1150 fdiv2:0 000, 001 97 na uvlo hysteresis v uvlo (v dd =1.55v) ? (v dd _ shutdown voltage ) 150 250 mv fout, pwmout rise time t rise see note 2, c l = 15pf 10 ns fout, pwmout fall time t fall see note 2, c l = 15pf 10 ns fout jitter see note 3 0.001 % rset pin voltage v(rset) 0.3 v fdiv input current i fdiv 10 na -40c t a 85c 20 maximum oscillator frequency fosc rset= 360k 586 hz high level output voltage, fout and pwmout v dd - v oh i oh = 1ma 160 mv low level output voltage, fout and pwmout v ol i ol = 1ma 140 mv dead time t dt fout edge falling and pwmout edge rising 106 ns note 1: all devices are 100% production tested at t a = +25c and are guaranteed by characterization for t a = t min to t max , as specified. note 2: output rise and fall times are measured between the 10% and 90% of the v dd power-supply voltage levels. the specification is based on lab bench characterization and is not tested in production. note 3: timing jitter is the ratio of the peak-to-peak variation of the period to the mean of the period. the specification is based o n lab bench characterization and is not tested in production.
ts3005 page 4 ts3005 rev. 1.0 period - ms supply current - a 10.4 20.8 2 0 supply current vs fout period 0 31.2 3 4 1 41.6 52 supply voltage - volt period - ms 2.29 3.03 20.4 20.3 20.7 fout period vs supply voltage 1.55 3.77 20.5 20.6 4.51 c load - pf supply current - a 10 20 4 0 supply current vs c load(fout) 0 30 6 2 40 5.25 temperature - oc supply current - a 1.3 1.1 supply current vs temperature 1.4 1.5 1.2 -15 10 -40 35 60 85 supply voltage - volt start-up time - ms 16 15 19 start-up time vs supply voltage 17 18 20 temperature - oc period - ms -15 10 20 19.5 fout period vs temperature -40 35 20.5 60 85 21 21.5 typical performance characteristics v dd = 3v, v pwm_cntrl = v dd , r set = 4.32m ?, r load(fout) = open circuit, c load(fout) = 0pf, c load(pwm) = 0pf, cpwm = v dd , fdiv2:0 = 000 unless otherwise noted. values are at t a = 25c unless otherwise noted. 5 6 7 20.8 2.29 3.03 1.55 3.77 4.51 5.25 21
ts3005 ts3005 rev. 1.0 page 5 typical performance characteristics v dd = 3v, v pwm_cntrl = v dd , r set = 4.32m ?, r load(fout) = open circuit, c load(fout) = 0pf, c load(pwm) = 0pf, cpwm = v dd , fdiv2:0 = 000 unless otherwise noted. values are at t a = 25c unless otherwise noted. r set - m ? period - ms 2 4 20 0 50 period vs r set 0 6 30 40 10 8 10 percent of units - % supply current - a 0% supply current distribution 1.26 5% 10% 15% 20% 25% 30% 35% 1.3 1.34 1.38 fout and pwmout v dd = 3 v , c load = 15 p f, v pwm cntrl = v dd , c pwm = 10nf 5ms/div fout 2v/div pwmout 2v/div fout and pwmout v dd = 5 v , c load = 15 p f, v pwm cntrl = v dd , c pwm = 10nf 5ms/div fout 2v/div pwmout 2v/div fout v dd = 3v, c load = 15 p f 5ms/div fout v dd = 5v, c load = 15 p f 5ms/div fout 1v/div fout 1v/div 12 60
ts3005 page 6 ts3005 rev. 1.0 pin functions pin name function 1 fout fixed frequency output. a push-pull output stage with an output resistance of 160 ? . fout pin swings from gnd to vdd. for lowest power operation, capacitance loads should be minimized and resistive loads should be maximized. 2,3,4 fdiv2:0 frequency divider input. various combinations of these inputs will change the fout frequency for a fixed value of rset. refer to table 1. 5 pwmout pulse-width modulated output. a push-pull output stage with an output resistance of 160 ? , the pwmout pin is wired anti-phase with respect to fout and swings from gnd to vdd. for lowest power operation, capacitance loads should be minimized and resistive loads should be maximized. 6 pwm_cntrl pwm output pulse control pin. applying a voltage between gnd and v rset will reduce the duty cycle of the pwmout output that is set by the c apacitor connected to the cpwm pin. connect pwm_cntrl to vdd for fixed pwmout output pulse time (determined only by capacitor at cpwm). 7 gnd ground. connect this pin to the system?s analog ground plane. 8 cpwm pwmout pulse width programming capacitance input. a target capacitance connected from this pin to gnd sets the duty cycle of the pmw output. minimize any stray capacitance on this pin. the voltage on this pin will swing from gnd to v rset . connect cpwm to vdd to disable pwm function (saves pwm current). 9 vdd power supply voltage input. the supply voltage range is 1.55v v dd 5.25v. bypass this pin with a 0.1uf ceramic coupling capacitor in close proximity to the ts3005. 10 rset fout programming resistor input. a 4.32mohm resistor connected from this pin to ground sets the t3005?s internal oscillator?s output period to 20ms (49hz) . for optimal performance, the composition of the rset resistor shall be consistent with a tolerance of 1% or lower. the rset pin voltage is approximately 0.3v.
ts3005 ts3005 rev. 1.0 page 7 block diagram fdiv 2:0 t fout (s) fout (hz) i cpwm (a) 000 1.7ms-56.88ms 586-17.578 1 001 13.65ms-455.16ms 73.25-2.197 1 010 109.17ms-3.64 9.16-0.2746 100n 011 877.19ms-29.15 1.14-0.0343 100n 100 7.01-233.1 0.143-0.00429 100n 101 55.94-31.09min 0.0178-0.536mhz 100n 110 7.49min-4.146hrs 0.0022-0.0670mhz 100n 111 59.67min-33.1hrs 0.279mhz-8.381hz 100n table 1: fout and pwmout frequency range per fdiv2:0 combination
ts3005 page 8 ts3005 rev. 1.0 theory of operation the ts3005 is a user-pro grammable oscillator where the period of the square wave at its fout terminal is generated by an external resistor connected to the rset pin. the output period is given by: t fout (s) = 8 fdiv2:0 x rset x 512 1.08e11 equation 1. fout frequency calculation where fdiv2:0 = 0 to 7 with an r set = 4.32m ? and fdiv2:0=111, the fout period is approximately 715.88 minutes with a 50% duty cycle. as design aids, tables 2 lists ts3004?s typical fout period for various standard values for r set and fdiv2:0 = 111(7). the output period can be user-adjusted from 1.7ms to 33hrs without additional components. frequency divider inputs fdiv2:0 can be set to a logic state high or low in order to set the desired frequency as shown in to table 1. the ts3005 also provides a separate pwm output signal at its pwmout termi nal that is anti-phase with respect to fout. a dead time of approximately 106ns exists between fout and pwmout. to adjust the pulse width of the pwmout output, a single capacitor can be placed at the cpwm pin. to determine the capacitance needed for a desired pulse width, the following equation is to be used: cpwm(f)= pulse width(s) x i cpwm v cpwm ? 300mv equation 2. cpwm capacitor calculation where i cpwm and v cpwm is the current supplied and voltage applied to the cpwm capacitor, respectively. the pulse width is determi ned based on the period of fout and should never be greater than the period at fout. make sure the pwm_cntrl pin is set to at least 400mv when calculating the pulse width of pwmout. note v cpwm is approximately 300mv, which is the rset voltage. also note that i cpwm is either 1a or 100na. refer to table 1. the pwmout output pulse width can be adjusted further after selecting a cpwm capacitor this can be achieved by applying a voltage to the pwm_cntrl pin between v rset and gnd. with a voltage of at least v rset , the pulse width is set based on equation 2. for example, with a pe riod of 20.5ms( 49hz) a 10nf capacitor at the cpwm pin generates a pulse width of approximately 3ms. this can be calculated using equation 2. by reducing the pwm_cntrl voltage from v rset ? 300mv to gnd, the pulse width can be reduced further. note that as the fout frequency increases, the amount of pulse width reduction reduces and vice versa. furthermore, if the pwmout output is half the frequency of the fout output, this means your cpwm capacitor is too large and as a result, the pulse width is greater than the fout period. in this case, use equation 2 and reduce the capacitor value to less than the period. connect cpwm to vdd to disable the pwm function and in turn, save power. connect pwm_cntrl to vdd for a fixed pwmout out put pulse width, which is determined by the cpwm pin capacitor only. applications information minimizing power consumption to keep the ts3005?s power consumption low, resistive loads at the fout and pwmout terminals increase dc power consum ption and therefore should be as large as possible. capacitive loads at the fout and pwmout terminals increase the ts3005?s transient power consumption and, as well, should be as small as possible. one challenge to minimizing the ts3005?s transient power consumption is the probe capacitance of oscilloscopes and frequency counter instruments. most instruments exhibit an input capacitance of 15pf or more. unless buffered, the increase in transient load current can be as much as 400na. to minimize capacitive loading, the technique shown r set (m ?)t fout 0.360 59.67min 1 1.09hrs 2.49 6.87hrs 4.32 11.93hrs 6.81 18.81hrs 9.76 26.93hrs 12 33.1hrs table 2: t fout vs r set for fdiv2:0 = 111 ( 7 ) figure 1: using an external capacitor in series with probes reduces effective capacitive load. c ext = 1 1 c load(eff) - 1 c probe equation 3: external capacitor calculation
ts3005 ts3005 rev. 1.0 page 9 in figure 1 can be used. in this circuit, the principle of series-connected capacitors can be used to reduce the effective capacitive load at the ts3005?s fout and pwmout terminals. to determine the optimal value for c ext once the probe capacitance is known by simply solving for c ext using the following expression: for example, if the instrument?s input probe capacitance is 15pf and the desired effective load capacitance at either or both fout and pwmout terminals is to be 5pf, then the value of c ext should be 7.5pf. ts3005 start-up time as the ts3005 is powered up, its fout terminal (and pwmout terminal, if enabled) is active once the applied vdd is higher than 1.55v. once the applied vdd is higher than 1.55v, the master oscillator achieves steady -state operation within 18ms. 5 weeks and 5 days counter circuit with ts3005 the ts3005 can be configured into a 5 weeks and 5 days counter as shown in figure 2. the circuit is composed of a ts3005 timer and a dual 74vhc393 4-bit counter. the ts3005 divider inputs are set to fdiv2:0 = 111. with an rset of 11m ? , the fout period is approximately 30 hours. the complete circuit consumes approximately 4.5a and is powered with a single 3v cr2032 lithium button cell battery. if a shorter period is desired, a 10 day period is available via output 1qd. divide the pwmout output frequency by two with the ts3005 using a single resistor and capacitor, the ts3005 can be configured to a divide by two circuit as shown in figure 3. to achieve a divi de by two function with the ts3005, the pulse width of the pwmout output must be at least a factor of 2 greater than the period set at fout by resistor rset. the cpwm capacitor selected must meet this pulse width requirement and figure 3: configuring the ts3005 into a divide by two frequency divider figure 2: 5 weeks and 5 days counter circuit
ts3005 page 10 ts3005 rev. 1.0 can be calculated using equation 2. in figure 3, a value of 4.32m ? for rset sets the fout output period to 20.5ms. a cpwm capacitor of 0.1f was chosen, which sets the pulse width of pwmout to approximately 30ms. this is well above the required minimum pulse width of 20.5ms. flashing railroad lights with the ts3005 with only three resistors and two off the shelf leds, the ts3005 can be configured into a flashing railroad lights circuit. with the input divider set to fdiv2:0 = 010 and rset= 3.24m ? , the fout output frequency is 1hz. refer to figure 4. during the time the output is high, only the pull-down led is on while when the output is low, only the pull-up led is on. the supply voltage of the circuit is 5v. using the ts3005 and a potentiometer to dim an led the ts3005 can be configured to dim an led by modulating the pulse width of the pwmout output. with the input divider set to fdiv2:0 = 000 and rset= 2m ? , the fout output frequency is approximately 100hz (or 10ms period). refer to figure 5. the cpwm capaci tor was calculated using equation 2 with a pulse widt h of 8.1ms. to reduce the pulse width from 8.1ms and in turn, dim the led, a 1m ? potentiometer is used. the potentiometer is connected to the pwm_cntrl pin in a voltage divider configuration. the su pply voltage of the circuit is 5v. . figure 5: ts3005 configured to dim an led with a potentiometer figure 4: flashing railroad lights with the ts3005
ts3005 silicon laboratories, inc. page 11 400 west cesar chavez, austin, tx 78701 ts3005 rev. 1.0 +1 (512) 416-8500 ? www.silabs.com package outline drawing patent notice silicon labs invests in research and development to help our custom ers differentiate in the market with innovative low-power, s mall size, analog-intensive mixed-signal solutions. s ilicon labs' extensive patent portfolio is a testament to our unique approach and wor ld-class engineering team. the information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and om issions, and disclaims responsib ility for any consequences resu lting from the use of information included herein. additionally, silicon laborat ories assumes no responsibility for the functioning of undescr ibed features or parameters. silicon laboratories reserves the right to make c hanges without further notice. silicon laboratories makes no warra nty, representation or guarantee regarding the suitability of its pr oducts for any particular purpose, nor does silicon laboratories assume any liability arising out of the application or use of any product or circ uit, and specifically disclaims any and all liability, in cluding without limitation consequential or incidental damages. silicon laboratories products are not designed, intended, or authorized for use in applica tions intended to support or sustain life, or for any other application in wh ich the failure of the silicon laboratories product could create a situation where personal injury or death may occur. should buyer purchase or use silicon laboratories products for any such unintended or unaut horized application, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages. silicon laboratories and silicon labs are tr ademarks of silicon laboratories inc. other p roducts or brandnames mentioned herein are trademarks or re g istered trademarks of their res p ective holders. 10-pin tdfn33 package outline drawing (n.b., drawings are not to scale)
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